The present invention relates to a method for the manufacture of a coplanar, self-aligned field effect transistor. The method involves three masking levels and uses a thin film semiconductor. It is applicable to the field of large surface or area microelectronics and in particular to the control and addressing of a liquid crystal flat screen or an image sensor.
At present, the thin film semiconductor best suited to large surface or area devices is hydrogenated amorphous silicon. This is due to the low semiconductor deposition temperature, which makes it possible to use economic, transparent substrates, such as glass, as well as to the homogeneity of the deposited coating, even over large surfaces. However, the use of this material imposes four main constraints, which must be respected in order to obtain devices with optimum performance levels.
The first constraint is that the semiconductor and gate insulant coatings must be deposited consecutively and in the same enclosure, in order to maintain a good semiconductor - insulant interface quality. In the case of hydrogenated amorphous silicon (a-Si:H), this is generally respected because the devices used for depositing a-Si:H also make it possible to deposit the gate insulant without impairing the cleanness of the first deposit.
The second manufacturing constraint is the need to have good source and drain contacts, so that it is necessary to use a hydrogenated amorphous silicon coating highly doped in contact with the source and drain electrodes. Good quality source and drain contacts can be obtained by means of an intermediate a-Si:H coating doped during the deposit by adding a supplementary gas containing a doping element or by means of ion implantation.
The third manufacturing constraint is that as a result of the low conductivity of hydrogenated amorphous silicon, the distances between the channel and the source contact on the one hand and the drain contact on the other must be minimal. The source and drain contacts, as well as the gate must be defined in a precise manner (self-alignment of the electrodes), in order to reduce the stray capacitances occurring through the gate insulant. The source and drain contacts, as well as the gate must be located on the same side of the semiconductor coating, in order to eliminate the access resistance through the thickness of said coating. In most presently produced thin film transistors, the gate and the source and drain contacts partly overlap and are positioned on either side of the a-Si:H coating. A self-alignment method has recently been developed making it possible to produce thin film transistors with a staggered configuration, i.e. having the succession: substrate - gate - semiconductor insulant - drain and source contacts. This method is described in an article entitled "A self-alignment processed a-Si TFT matrix circuit for LCD panels" by ASMA et al in the Journal SID 83 Digest, pp. 144 and 145. The cutting of source and drain contacts in the n doped a-Si:H coating is carried out by irradiation from the substrate, which makes it possible for the gate to serve as a mask. This procedure is only applicable to the type of structure in which the gate and contacts are on either side of the a-Si:H coating, which must be sufficiently thin to be transparent.
The fourth manufacturing constraint is constituted by the number of masking levels. Four masking levels are generally used for the manufacture of a-Si:H thin film transistors, whereas three levels are sufficient in the self-aligned method. In order to increase the manufacturing efficiency and reduce its costs, it is necessary to limit the number of masking levels to the strict minimum. Hitherto, none of the known methods make it possible to satisfy the four aforementioned constraints. The manufacturing method according to the invention satisfies these constraints by self-alignment and ion implantation techniques. It makes it possible to reduce the number of masking levels to three.